NEC Network Controller uPD98502 - Manual (Page 503)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM 503
LBU
Load Byte Unsigned
LBU
base
LBU
1 0 0 1 0 0
rt offset
31 26 25 21 20 16 15 0
6 5 5 16
Format:
LBU rt, offset (base)
Description:
The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address.
The contents of the byte at the memory location specified by the effective address are zero-extended and loaded
into general register rt.
Operation:
32 T: vAddr ← ((offset
15
)
16
|| offset
15..0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE - 1..3
|| (pAddr
2..0
xor ReverseEndian
3
)
mem ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr
2..0
xor BigEndianCPU
3
GPR [rt] ← 0 24 || mem
7 + 8* byte..8* byte
64 T: vAddr ← ((offset
15
) 48 || offset
15..0
) + GPR [base]
(pAddr, uncached)
← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE - 1..3
|| (pAddr
2..0
xor ReverseEndian 3 )
mem
← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr
2..0
xor BigEndianCPU
3
GPR [rt]
← 0 56
|| mem
7 + 8* byte..8* byte
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception