Shift right arithmetic – NEC Network Controller uPD98502 User Manual
Page 553
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
553
SRA
Shift Right Arithmetic
SRA
0
0 0 0 0 0
SPECIAL
0 0 0 0 0 0
rt
rd
sa
SRA
0 0 0 0 1 1
31
26 25
21 20
16 15
11 10
6 5
0
6
5
5
5
5
6
Format:
SRA rd, rt, sa
Description:
The contents of general register
rt are shifted right by sa bits, sign-extending the high-order bits.
The result is placed in register
rd.
In 64-bit mode, the operand must be a valid sign-extended, 32-bit value.
Operation:
32
T:
GPR [rd]
← (GPR [rt]
31
)
sa
|| GPR [rt]
31...sa
64
T:
s
← 0 || sa
temp
← (GPR [rt]
31
)
s
|| GPR [rt]
31...s
GPR [rd]
← (temp
31
)
32
|| temp
Exceptions:
None