NEC Network Controller uPD98502 - Manual (Page 9)

Preliminary User’s Manual S15543EJ1V0UM 9
CHAPTER 3 SYSTEM CONTROLLER............................................................................................... 185
3.1 Overview ................................................................................................................................... 185
3.1.1 CPU interface ..............................................................................................................................185
3.1.2 Memory interface .........................................................................................................................185
3.1.3 IBUS Interface .............................................................................................................................185
3.1.4 UART...........................................................................................................................................186
3.1.5 EEPROM .....................................................................................................................................186
3.1.6 Timer ...........................................................................................................................................186
3.1.7 Interrupt controller .......................................................................................................................186
3.1.8 DSU (Deadman’s SW Unit) .........................................................................................................186
3.1.9 System block diagram .................................................................................................................187
3.1.10 Data flow diagram........................................................................................................................188
3.2 Registers................................................................................................................................... 189
3.2.1 Register map ...............................................................................................................................189
3.2.2 S_GMR (General Mode Register) ...............................................................................................191
3.2.3 S_GSR (General Status Register) ...............................................................................................191
3.2.4 S_ISR (Interrupt Status Register) ................................................................................................192
3.2.5 S_IMR (Interrupt Mask Register) .................................................................................................193
3.2.6 S_NSR (NMI Status Register) .....................................................................................................194
3.2.7 S_NER (NMI Enable Register) ....................................................................................................195
3.2.8 S_VER (Version Register) ...........................................................................................................195
3.2.9 S_IOR (IO Port Register).............................................................................................................196
3.2.10 S_WRCR (Warm Reset Control Register) ...................................................................................197
3.2.11 S_WRSR (Warm Reset Status Register).....................................................................................198
3.2.12 S_PWCR (Power Control Register) .............................................................................................199
3.2.13 S_PWSR (Power Status Register) ..............................................................................................200
3.3 CPU Interface ........................................................................................................................... 201
3.3.1 Overview......................................................................................................................................201
3.3.2 Data rate control ..........................................................................................................................201
3.3.3 Burst size control .........................................................................................................................201
3.3.4 Address decoding ........................................................................................................................201
3.3.5 Endian conversion .......................................................................................................................201
3.3.6 I/O performance...........................................................................................................................203
3.4 Memory Interface ..................................................................................................................... 204
3.4.1 Overview......................................................................................................................................204
3.4.2 Memory regions ...........................................................................................................................204
3.4.3 Memory signal connections .........................................................................................................205
3.4.4 Memory performance...................................................................................................................206
3.4.5 RMMDR (ROM Mode Register) ...................................................................................................207
3.4.6 RMATR (ROM Access Timing Register)......................................................................................207
3.4.7 SDMDR (SDRAM Mode Register) ...............................................................................................209
3.4.8 SDTSR (SDRAM Type Selection Register) .................................................................................210
3.4.9 SDPTR (SDRAM Precharge Timing Register).............................................................................211
3.4.10 SDRMR (SDRAM Refresh Mode Register) .................................................................................211
3.4.11 SDRCR (SDRAM Refresh Timer Count Register) .......................................................................212
3.4.12 MBCR (Memory Bus Control Register)........................................................................................212
3.4.13 Boot ROM....................................................................................................................................213
3.4.14 SDRAM........................................................................................................................................216