NEC Network Controller uPD98502 - Manual (Page 476)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
476 Preliminary User’s Manual S15543EJ1V0UM
DIVU
Divide Unsigned
DIVU
rs
SPECIAL
0 0 0 0 0 0
rt
0
0 0 0 0 0 0 0 0 0 0
31 26 25 21 20 16 15 0
6 5 5 10
DIVU
0 1 1 0 1 1
6 5
6
Format:
DIVU rs, rt
Description:
The contents of general register rs are divided by the contents of general register rt, treating both operands as
unsigned values. No integer overflow exception occurs under any circumstances, and the result of this operation is
undefined when the divisor is zero.
In 64-bit mode, the operands must be valid sign-extended, 32-bit values.
This instruction is typically followed by additional instructions to check for a zero divisor.
When the operation completes, the quotient word of the double result is loaded into special register LO, and the
remainder word of the double result is loaded into special register HI.
If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined. Correct
operation requires separating reads of HI or LO from writes by two or more instructions.
Operation:
32 T-2: LO ← undefined
HI ← undefined
T-1: LO ← undefined
HI ← undefined
T: LO ← (0 || GPR [rs]) div (0 || GPR [rt])
HI ← 0 || GPR [rs]) mod (0 || GPR [rt])
64 T-2: LO ← undefined
HI ← undefined
T-1: LO ← undefined
HI ← undefined
T: q ← (0 || GPR [rs]
31..0
) div (0 || GPR [rt]
31..0
)
r ← (0 || GPR [rs]
31..0
) mod (0 || GPR [rt]
31..0
)
LO ← (q
31
)
32
|| q
31..0
HI ← (r
31
) 32 || r
31..0
Exceptions:
None