NEC Network Controller uPD98502 - Manual (Page 520)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
520 Preliminary User’s Manual S15543EJ1V0UM
LWR
Load Word Right (3/3)
LWR
Given a word in a register and a word in memory, the operation of LWR is as follows:
B C D E F G A H
J K L M N O I P
Register
Memory
LWR
vAddr2..0 Destination Type Offset
(LEM)
0
1
2
3
4
5
6
7
S S S S MN O P
S S S S E M N O
S S S S E F M N
S S S S E F GM
S S S S I J K L
S S S S E I J K
S S S S E F I J
S S S S E F G I
3
2
1
0
3
2
1
0
0
1
2
3
4
5
6
7
Remark LEM Little-endian memory (BigEndianMem = 0)
Type AccessType (see Table 2-3. Byte Specification Related to Load and Store Instructions)
sent to memory
Offset pAddr2..0 sent to memory
S sign-extend of destination31
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception