NEC Network Controller uPD98502 - Manual (Page 207)

CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 207
3.4.5 RMMDR (ROM Mode Register)
The ROM mode register “RMMDR” is a read-write and 32-bit word-aligned register. RMMDR is used to setup the
PROM/flash memory interface. RMMDR is initialized to 0 at reset and contains the following fields:
Bits Field R/W Default Description
31:9 Reserved R/W 0 Hardwired to 0.
8 WM R/W 0 Write mask:
0 = masked. Flash data is protected from unintentional write.
1 = not masked. Flash data is not protected.
7:2 Reserved R/W 0 Hardwired to 0.
1:0 FSM R/W 00 Flash/PROM size model:
00 = mode1 (4-MByte mode)
01 = mode2 (8-MByte mode)
10 = mode3 (1-MByte mode)
11 = mode4 (2-MByte mode)
Remark Don’t change the value on the FSM field after setting a value into the FSM field.
3.4.6 RMATR (ROM Access Timing Register)
The ROM access timing register “RMATR” is a read-write and 32-bit word-aligned register. RMATR is used to set
the access time in the PROM/flash interface. RMATR is initialized to 0 at reset and contains the following fields:
Bits Field R/W Default Description
31:3 Reserved R/W 0 Hardwired to 0.
Flash/PROM access timing for normal ROM: 2:0 FAT R/W 000
000 = 18 clocks
001 = 4 clocks
010 = 6 clocks
011 = 8 clocks
100 = 10 clocks
101 = 12 clocks
110 = 14 clocks
111 = 16 clocks
66 MHz: 272.4 ns
66 MHz: 60.6 ns
66 MHz: 90.9 ns
66 MHz: 121.2 ns
66 MHz: 151.5 ns
66 MHz: 181.8 ns
66 MHz: 212.1 ns
66 MHz: 242.4 ns
100 MHz: 180 ns
100 MHz: 40 ns
100 MHz: 60 ns
100 MHz: 80 ns
100 MHz: 100 ns
100 MHz: 120 ns
100 MHz: 140 ns
100 MHz: 160 ns
Remark ROM access timing is depended on the system clock frequency.