NEC Network Controller uPD98502 User Manual
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CHAPTER 2 V
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Preliminary User’s Manual S15543EJ1V0UM
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2.5.4.16 Watch exception
(1) Cause
A Watch exception occurs when a load or store instruction references the physical address specified by the
WatchLo/WatchHi registers. The WatchLo/WatchHi registers specify whether a load or store or both could have
initiated this exception.
• When the R bit of the WatchLo register is set to 1: Load instruction
• When the W bit of the WatchLo register is set to 1: Store instruction
• When both the R bit and W bit of the WatchLo register are set to 1: Load instruction or store instruction
The CACHE instruction never causes a Watch exception.
The Watch exception is postponed while the EXL bit in the Status register is set to 1, and Watch exception is only
maskable by setting the EXL bit in the Status register to 1.
(2) Processing
The common exception vector is used for this exception, and the Watch code in the ExcCode field of the Cause
register is set.
The EPC register contains the address of the instruction that caused the exception. However, if this instruction is
in a branch delay slot, the EPC register contains the address of the preceding jump or branch instruction, and the
BD bit of the Cause register is set to 1.
(3) Servicing
The Watch exception is a debugging aid; typically the exception handler transfers control to a debugger, allowing
the user to examine the situation. To continue, once the Watch exception must be disabled to execute the faulting
instruction. The Watch exception must then be reenabled. The faulting instruction can be executed either by the
debugger or by setting breakpoints.