NEC Network Controller uPD98502 - Manual (Page 21)

Preliminary User’s Manual S15543EJ1V0UM 21
LIST OF TABLES (1/2)
Table No. Title Page
2-1 System Control Coprocessor (CP0) Register Definitions...............................................................................64
2-2 Number of Delay Slot Cycles Necessary for Load and Store Instructions .....................................................67
2-3 Byte Specification Related to Load and Store Instructions ............................................................................68
2-4 Load/Store Instruction....................................................................................................................................69
2-5 Load/Store Instruction (Extended ISA) ..........................................................................................................70
2-6 ALU Immediate Instruction ............................................................................................................................71
2-7 ALU Immediate Instruction (Extended ISA) ...................................................................................................72
2-8 Three-Operand Type Instruction....................................................................................................................72
2-9 Three-Operand Type Instruction (Extended ISA)...........................................................................................73
2-10 Shift Instruction ..............................................................................................................................................73
2-11 Shift Instruction (Extended ISA).....................................................................................................................74
2-12 Multiply/Divide Instructions ............................................................................................................................75
2-13 Multiply/Divide Instructions (Extended ISA) ...................................................................................................76
2-14 Number of Stall Cycles in Multiply and Divide Instructions ............................................................................77
2-15 Number of Delay Slot Cycles in Jump and Branch Instructions .....................................................................77
2-16 Jump Instruction ............................................................................................................................................78
2-17 Branch Instructions ........................................................................................................................................79
2-18 Branch Instructions (Extended ISA)...............................................................................................................80
2-19 Special Instructions........................................................................................................................................81
2-20 Special Instructions (Extended ISA) (1/2) ......................................................................................................81
2-20 Special Instructions (Extended ISA) (2/2) ......................................................................................................82
2-21 System Control Coprocessor (CP0) Instructions (1/2) ...................................................................................82
2-21 System Control Coprocessor (CP0) Instructions (2/2) ...................................................................................83
2-22 Operation in Each Stage of Pipeline (MIPS III) ..............................................................................................86
2-23 Correspondence of Pipeline Stage to Interlock and Exception Conditions ....................................................94
2-24 Pipeline Interlock ...........................................................................................................................................95
2-25 Description of Pipeline Exception ..................................................................................................................95
2-26 VR Series Supported Instructions................................................................................................................100
2-27 Comparison of useg and xuseg ...................................................................................................................107
2-28 32-bit and 64-bit Supervisor Mode Segments..............................................................................................109
2-29 32-bit Kernel Mode Segments .....................................................................................................................112
2-30 64-bit Kernel Mode Segments .....................................................................................................................113
2-31 Cacheability and xkphys Address Space .....................................................................................................114
2-32 Cache Algorithm ..........................................................................................................................................121
2-33 Mask Values and Page Sizes ......................................................................................................................121
2-34 CP0 Exception Processing Registers ..........................................................................................................130
2-35 Cause Register Exception Code Field .........................................................................................................137
2-36 64-Bit Mode Exception Vector Base Addresses ..........................................................................................142
2-37 32-Bit Mode Exception Vector Base Addresses ..........................................................................................143
2-38 Exception Priority Order...............................................................................................................................144