NEC Network Controller uPD98502 - Manual (Page 58)

CHAPTER 2 V R 4120A
58 Preliminary User’s Manual S15543EJ1V0UM
2.1.1 Internal block configuration
2.1.1.1 CPU
CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit integer data
bus, and multiply-and-accumulate operation unit.
2.1.1.2 Coprocessor 0 (CP0)
CP0 incorporates a memory management unit (MMU) and exception handling function. MMU checks whether
there is an access between different memory segments (user, supervisor, and kernel) by executing address
conversion. The translation lookaside buffer (TLB) converts virtual addresses to physical addresses.
2.1.1.3 Instruction cache
The instruction cache employs direct mapping, virtual index, and physical tag. Its capacity is 16 Kbytes.
2.1.1.4 Data cache
The data cache employs direct mapping, virtual index, physical tag, and write back. Its capacity is 8 Kbytes.
2.1.1.5 CPU bus interface
The CPU bus interface controls data transmission/reception between the V R 4120A and the BCU, which is one of
peripheral units. The V R 4120A interface consists of two 32-bit multiplexed address/data buses (one is for input, and
another is for output), clock signals, and control signals such as interrupts.