NEC Network Controller uPD98502 - Manual (Page 238)

CHAPTER 4 ATM CELL PROCESSOR
238 Preliminary User’s Manual S15543EJ1V0UM
4.4 Registers for ATM Cell Processing
Registers in ATM Cell Processor block can be classified into 3 groups: SAR registers, DMA registers and FIFO
Control registers. These registers can be accessed both V
R
4120A and RISC Core in ATM Cell Processor.
4.4.1 Register map
Registers are used for SAR functions. V R 4120A writes to these registers to control SAR functions and reads from
these registers to know the status. F/W on RISC Core reads these registers to know indication from V R 4120A and
writes to these registers to indicate the status of ATM Cell Processor.
4.4.1.1 Direct addressing register
From the V R 4120A’s point of view, 1001_0000H is the Base Address to access the registers in ATM Cell
Processor.
Offset Address Register Name R/W Access Description
1001_F000H A_GMR R/W W General Mode Register
1001_F004H A_GSR RC W General Status Register
1001_F008H A_IMR R/W W Interrupt Mask Register
1001_F00CH A_RQU R W Receive Queue Underrun Register
1001_F010H A_RQA R W Receive Queue Alert Register
1001_F014H N/A - - Reserved for future use
1001_F018H A_VER R W Version Register
1001_F01CH N/A - - Reserved for future use
1001_F020H A_CMR R/W W Command Register
1001_F024H N/A - - Reserved for future use
1001_F028H A_CER R/W W Command Extension Register
1001_F02CH:
1001_F04CH
N/A - - Reserved for future use
1001_F050H A_MSA0 R/W W Mailbox0 Start Address Register
1001_F054H A_MSA1 R/W W Mailbox1 Start Address Register
1001_F058H A_MSA2 R/W W Mailbox2 Start Address Register
1001_F05CH A_MSA3 R/W W Mailbox3 Start Address Register
1001_F060H A_MBA0 R/W W Mailbox0 Bottom Address Register
1001_F064H A_MBA1 R/W W Mailbox1 Bottom Address Register
1001_F068H A_MBA2 R/W W Mailbox2 Bottom Address Register
1001_F06CH A_MBA3 R/W W Mailbox3 Bottom Address Register
1001_F070H A_MTA0 R/W W Mailbox0 Tail Address Register
1001_F074H A_MTA1 R/W W Mailbox1 Tail Address Register
1001_F078H A_MTA2 R/W W Mailbox2 Tail Address Register
1001_F07CH A_MTA3 R/W W Mailbox3 Tail Address Register
1001_F080H A_MWA0 R/W W Mailbox0 Write Address Register
1001_F084H A_MWA1 R/W W Mailbox1 Write Address Register
1001_F088H A_MWA2 R/W W Mailbox2 Write Address Register
1001_F08CH A_MWA3 R/W W Mailbox3 Write Address Register
1001_F090H A_RCC R W Valid Received Cell Counter
1001_F094H A_TCC R W Valid Transmitted Cell Counter
1001_F098H A_RUEC R W Receive Unprovisioned VPI/VCI Error Cell Counter
1001_F09CH A_RIDC R W Receive Internal Dropped Cell Counter
1001_F0A0H:
1001_F0BCH
N/A - - Reserved for future use
1001_F0C0H A_T1R R/W W T1 Time Register
1001_F0C4H N/A - - Reserved for future use