NEC Network Controller uPD98502 - Manual (Page 108)

CHAPTER 2 V R 4120A
108 Preliminary User’s Manual S15543EJ1V0UM
2.4.2.6 Supervisor-mode virtual addressing
Supervisor mode shown in Figure 2-29 is designed for layered operating systems in which a true kernel runs in
Kernel mode, and the rest of the operating system runs in Supervisor mode.
The processor operates in Supervisor mode when the Status register contains the following bit-values:
— KSU = 01
— EXL = 0
— ERL = 0
In conjunction with these bits, the SX bit in the Status register selects Supervisor mode addressing:
— When SX = 0: 32-bit supervisor space is selected.
— When SX = 1: 64-bit supervisor space is selected.
Figure 2-29 shows the supervisor mode address mapping, and Table 2-28 lists the characteristics of the
Supervisor mode segments.
Figure 2-29. Supervisor Mode Address Space
64-bit mode 32-bit mode
Note
DFFF_FFFFH
E000_0000H
C000_0000H
FFFF_FFFFH
Address error
FFFF_FFFF_FFFF_FFFFH
suseg
sseg
7FFF_FFFFH
0000_0000H
8000_0000H
xsuseg
xsseg
csseg
BFFF_FFFFH
4000_00FF_FFFF_FFFFH
4000_0100_0000_0000H
0.5 Gbytes with
TLB mapping
Address error
2 Gbytes with TLB
mapping
Address error
0.5 Gbytes with
TLB mapping
Address error
1 Tbyte with TLB
mapping
Address error
1 Tbyte with TLB
mapping
FFFF_FFFF_E000_0000H
FFFF_FFFF_DFFF_FFFFH
FFFF_FFFF_C000_0000H
FFFF_FFFF_BFFF_FFFFH
3FFF_FFFF_FFFF_FFFFH
4000_0000_0000_0000H
0000_0000_0000_0000H
0000_00FF_FFFF_FFFFH
0000_0100_0000_0000H
Note The V R 4120A uses 64-bit addresses within it. For 32-bit mode addressing, bit 31 is sign-extended to bits
32 to 63, and the resulting 32 bits are used for addressing. Usually, it is impossible for 32-bit mode
programs to generate invalid addresses. In an operation of base register + offset for addressing, however,
a two's complement overflow may occur, causing an invalid address. Note that the result becomes
undefined. Two factors that can cause a two’s complement follow:
— When offset bit 15 is 0, base register bit 31 is 0, and bit 31 of the operation “base register + offset” is 1
— When offset bit 15 is 1, base register bit 31 is 1, and bit 31 of the operation “base register + offset” is 0