NEC Network Controller uPD98502 User Manual
Page 124
CHAPTER 2 V
R
4120A
124
Preliminary User’s Manual S15543EJ1V0UM
2.4.5.8 Config register (16)
The Config register specifies various configuration options selected on V
R
4120A processors.
Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and
are included in the Config register as read-only status bits for the software to access. Other configuration options are
read/write (AD, EP, and K0 fields) and controlled by software; on Cold Reset these fields are undefined. Since only a
subset of the V
R
4000 Series options are available in the V
R
4120A, some bits are set to constants (e.g., bits 14:13)
that were variable in the V
R
4000 Series. The Config register should be initialized by software before caches are used.
Figure 2-42 shows the format of the Config register.
Figure 2-42. Config Register Format
1
1
2
2
1
23
1
1
2
19
20
21
22
17
18
15
16
14
1
3
4
28
30
24
27
31
0
EC
EP
0
AD
AD
AD
1
0
BE
13
10
1
12
CS
3
11
9
IC
3
8
6
DC
2
5
3
0
3
2
0
K0
0
0 M16
IB
4
1
EC : Frequency ratio of system interface clock (VTCLK) (read only)
0 to 6
→ RFU
7
→ Pipeline clock (ACLK) frequency /1
EP : Transfer data pattern (cache write-back pattern) setting
0
→ DD: 1 Word/1 Cycle
Others
→ RFU: Do not set
AD : Accelerate data mode
0
→ V
R
4000 Series compatible mode
1
→ RFU
M16: MIPS16 ISA mode enable/disable indication (read only)
0
→ MIPS16 instruction cannot be executed (The
µPD98502 sets “0” in this bit because it does not support
MIPS16 mode).
1
→ MIPS16 instruction can be executed.
BE : BigEndianMem. Endian mode of memory and a kernel.
0
→ Little endian
1
→ Big endian
CS : Cache size mode indication (fixed to 1 in the V
R
4120A)
0
→ IC = 2
(n+12)
Bytes, DC = 2
(n+12)
Bytes
1
→ IC = 2
(n+10)
Bytes, DC = 2
(n+10)
Bytes
IC : Instruction cache size indication. In the V
R
4120A, 2
(IC+10)
bytes.
4
→ 16 Kbytes
Others
→ RFU
DC : Data cache size indication. In the V
R
4120A, 2
(DC+10)
bytes.
3
→ 8 Kbytes
Others
→ RFU
IB : Select refill size (In this LSI, 8-word mode is not supported)
0
→ 4 words (16 bytes)
1
→ Do not set. (8 words (32 bytes))
K0 : kseg0 cache coherency algorithm
010
→ Uncached
Others
→ Cached
1
: 1 is returned when read.
0
: 0 is returned when read.
Caution
Be sure to set the EP field, the AD bit and the IB bit to 0. If they are set with any other values,
the processor may behave unexpectedly.