NEC Network Controller uPD98502 - Manual (Page 65)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 65
2.1.7 CPU core memory management system (MMU)
The V R 4120A has a 32-bit physical addressing range of 4 Gbytes. However, since it is rare for systems to
implement a physical memory space as large as that memory space, the CPU provides a logical expansion of
memory space by translating addresses composed in the large virtual address space into available physical memory
addresses. The V
R
4120A supports the following two addressing modes:
• 32-bit mode, in which the virtual address space is divided into 2 Gbytes for user process and 2 Gbytes for the
kernel.
• 64-bit mode, in which the virtual address is expanded to1 Tbyte (2 40
bytes) of user virtual address space.
A detailed description of these address spaces is given in Section 2.4 Memory Management System.
2.1.8 Translation lookaside buffer (TLB)
Virtual memory mapping is performed using the translation lookaside buffer (TLB). The TLB converts virtual
addresses to physical addresses. It runs by a full-associative method. It has 32 entries, each mapping a pair of
pages having a variable size (1 KB to 256 KB).
2.1.8.1 Joint TLB (JTLB)
JTLB holds both an instruction address and data address.
For fast virtual-to-physical address decoding, the V
R
4120A uses a large, fully associative TLB (joint TLB) that
translates 64 virtual pages to their corresponding physical addresses. The TLB is organized as 32 pairs of even-odd
entries, and maps a virtual address and address space identifier (ASID) into the 4-Gbyte physical address space.
The page size can be configured, on a per-entry basis, to map a page size of 1 KB to 256 KB. A CP0 register
stores the size of the page to be mapped, and that size is entered into the TLB when a new entry is written. Thus,
operating systems can provide special purpose maps; for example, a typical frame buffer can be memory-mapped
using only one TLB entry.
Translating a virtual address to a physical address begins by comparing the virtual address from the processor with
the physical addresses in the TLB; there is a match when the virtual page number (VPN) of the address is the same
as the VPN field of the entry, and either the Global (G) bit of the TLB entry is set, or the ASID field of the virtual
address is the same as the ASID field of the TLB entry.
This match is referred to as a TLB hit. If there is no match, a TLB Miss exception is taken by the processor and
software is allowed to refill the TLB from a page table of virtual/physical addresses in memory.
2.1.9 Operating modes
The V R 4120A has three operating modes:
— User mode
— Supervisor mode
— Kernel mode
The manner in which memory addresses are translated or mapped depends on these operating modes. Refer to
Section 2.4 Memory Management System for details.
2.1.10 Cache
The V
R
4120A chip incorporates instruction and data caches, which are independent of each other. This
configuration enables high-performance pipeline operations. Both caches have a 64-bit data bus, enabling a one-
clock access. These buses can be accessed in parallel. The instruction cache of the V
R
4120A has a storage
capacity of 16 KB, while the data cache has a capacity of 8 KB.
A detailed description of caches is given in Section 2.7 Cache Memory.