Motorola MPC8260 - Manual (Page 993)

MOTOROLA Index Index-13
INDEX
serial peripheral interace (SPI)
master mode, 33-3
slow go, 17-2
transparent mode
overview, 32-1
serial communications controllers (SCCs), 23-1
serial management controllers (SMCs), 26-20
UART mode
serial communications controllers (SCCs), 20-1
serial management controllers (SMCs), 26-10
MPTPR (memory refresh timer prescaler
register), 10-32
Multi-channel controllers (MCCs)
CHAMR
HDLC mode, 27-10
transparent mode, 27-13
channel extra parameters, 27-5
commands, 27-16
data structure organization, 27-2
exceptions, 27-17
features list, 27-1
global parameters, 27-3
HDLC parameters (channel-specific), 27-8
initialization, 27-24
INTMSK, 27-9
latency, 27-26
MCCE, 27-18
MCCFx, 27-15
MCCM, 27-18
parameters for transparent operation, 27-12
performance, 27-26
receive commands, 27-17
RSTATE, 27-11
RxBD, 27-21
super channel table, 27-5
TSTATE, 27-9
TxBD, 27-23
MxMR (machine x mode registers), 10-26
N
NMSI (non-multiplexed serial interface)
configuration, 15-4
SMC NMSI connection, receive and transmit, 26-2
synchronization in NMSI mode,
transparent operation, 23-3
O
Operations
atomic bus operation, 10-10
digital phase-locked loop (DPLL) operation, 19-22
SMC buffer descriptor, 26-5
transparent operation, NMSI sychronization, 23-3
ORx (option registers), 10-16
P
Parallel I/O ports
block diagram, 35-6
features, 35-1
overview, 35-1
PDATx, 35-2
PDIRx, 35-3
pin assignments (port AÐport D), 35-8Ð35-19
PODRx, 35-2
port C interrupts, 35-19
port pin functions, 35-6
PPAR, 35-4
programming options, 35-8
PSORx, 35-4
registers, 35-2
Parameter RAM
ATM controller, 29-37
fast communications controllers (FCCs)
Fast Ethernet mode, 30-9
HDLC mode, 31-4
overview, 28-10
HDLC mode, 21-3
I
2
C controller, 34-9
IDMA emulation, 18-16
serial communications controllers (SCCs)
all protocols, 19-13
base addresses, 19-15
BISYNC mode, 22-3
overview, 19-13
UART mode, 20-4
serial management controllers (SMCs)
GCI mode, 26-30
overview, 26-6, 26-30
transparent mode, 26-6
UART mode, 26-6
serial peripheral interface (SPI), 33-10
Parity byte select (PBSE), 10-11
PDATx (port data) registers, 35-2
PDIRx (port data direction registers), 35-3
PDTEA (SDMA 60x bus transfer error address
register), 18-4
PDTEM (SDMA 60x bus transfer error MSNUM
register), 18-4
PISCR (periodic interrupt status and control
register), 4-42
PITC (periodic interrupt timer count register), 4-43
PITR (periodic interrupt timer register), 4-44
PODRx (port open-drain registers), 35-2
Power consumption
FCCs, 28-21
SCCs, 19-27
PPAR (port pin assignment register), 35-4
PPC_ACR (60x bus arbiter configuration
register), 4-28