Motorola MPC8260 - Manual (Page 914)

31-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
The RxBD status bits are written by the HDLC controller after receiving the associated data
buffer.
The remaining RxBD parameters are as follows:
¥ Data length is the number of octets the CP writes into this BDÕs data buffer. It is
written by the CP once the BD is closed. When this is the last BD in the frame (L =
1), this Þeld contains the total number of frame octets, including 2 or 4 bytes for
CRC. The memory allocated for this buffer should be no smaller than the MRBLR
value.
¥ Rx data buffer pointer. The receive buffer pointer, which always points to the Þrst
location of the associated data buffer, resides in internal or external memory and
must be divisible by 32 unless FPSMR[TS] = 1 (see Table 31-6).
31.8 HDLC Transmit Buffer Descriptor (TxBD)
Data is presented to the HDLC controller for transmission on an FCC channel by arranging
it in buffers referenced by the channel TxBD table. The HDLC controller conÞrms
transmission (or indicates errors) using the BDs to inform the core that the buffers have
been serviced. Figure 31-6 shows the FCC HDLC TxBD.
11 NO Rx nonoctet-aligned frame. Set when a received frame contains a number of bits not divisible by
eight.
12 AB Rx abort sequence. At least seven consecutive 1s are received during frame reception.
13 CR Rx CRC error. This frame contains a CRC error. Received CRC bytes are written to the receive
buffer.
14 OV Overrun. A receiver overrun occurs during frame reception.
15 CD Carrier detect lost. CD has negated during frame reception. This bit is valid only for NMSI mode.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 R Ñ W I L TC CM Ñ UN CT
Offset + 2 Data Length
Offset + 4 Tx Data Buffer Pointer
Offset + 6
Figure 31-6. FCC HDLC Transmit Buffer Descriptor (TxBD)
Table 31-7. RxBD field Descriptions (Continued)
Bits Name Description