Motorola MPC8260 - Manual (Page 730)

26-34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Table 26-22 describes SMC C/I channel TxBD Þelds.
26.5.9 SMC GCI Event Register (SMCE)/Mask Register (SMCM)
The SMCE generates interrupts and report events recognized by the SMC channel. When
an event is recognized, the SMC sets its corresponding SMCE bit. SMCE bits are cleared
by writing ones; writing zeros has no effect. SMCM has the same bit format as SMCE.
Setting an SMCM bit enables, and clearing an SMCM bit disables, the corresponding
interrupt. Unmasked bits must be cleared before the CP clears the internal interrupt request
to the SIU interrupt controller.
Table 26-23 describes SMCE/SMCM Þelds.
Table 26-22. SMC C/I Channel TxBD Field Descriptions
Bits Name Description
0 R Ready.
0 Cleared by the CP after transmission to indicate that the BD is available to the core.
1 Set by the core when data associated with this BD is ready for transmission.
1Р7 С Reserved, should be cleared.
8Ð13 C/I DATA Command/indication data bits. For C/I channel 0, bits 10Ð13 hold the 4-bit data Þeld (bits 8 and 9
are always written with zeros). For C/I channel 1, bits 8Ð13 contain the 6-bit data Þeld.
14Р15 С Reserved, should be cleared.
Bit 0 1 2 3 4 5 6 7
Field Ñ CTXB CRXB MTXB MRXB
Reset 0000_0000
R/W R/W
Address 0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2)
Figure 26-19. SMC GCI Event Register (SMCE)/Mask Register (SMCM)
Table 26-23. SMCE/SMCM Field Descriptions
Bits Name Description
0Р3 С Reserved, should be cleared.
4 CTXB C/I channel buffer transmitted. Set when the C/I transmit buffer is now empty.
5 CRXB C/I channel buffer received. Set when the C/I receive buffer is full.
6 MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer is now empty.
7 MRXB Monitor channel buffer received. Set when the monitor receive buffer is full.