Motorola MPC8260 - Manual (Page 279)

MOTOROLA Chapter 10. Memory Controller 10-3
Part III. The Hardware Interface
Figure 10-1. Dual-Bus Architecture
10.1 Features
The memory controllerÕs main features are as follows:
¥ Twelve memory banks
Ñ 32-bit address decoding with mask
Ñ Variable block sizes (32 Kbytes to 4 Gbytes)
Ñ Three types of data errors check/correction:
Ð Normal odd/even parity
Ð Read-modify-write (RMW) odd/even parity for single accesses
Ð ECC
MPC8260
A[0Ð31]
D[0Ð63]
LA[14Ð31]
LD[0Ð31]
External
Master
60x
Local
60x Memory
Control Signals
CS[0Ð11]
Local Memory
Control Signals
60x Address
Bus Interface
Local Address
Bus Interface
Local Data
Bus Interface
60x Address [0Ð31]
Local Address [0Ð31]
60x Data[0Ð63]
Local Data [0Ð63]
GPCM
SDRAM
Local
Memory
Controller
SDRAM
GPCM
60x
Memory
Controller
3 UPM
Arrays
Address Decoders
Local
60x-to-Local
Core
CPM/Local
2
®
1
60x
Transactions
60x Data
Bus Interface
CPM/PCI
Master
Slave
Slave
Memory
Devices
Memory
Devices