Motorola MPC8260 - Manual (Page 389)

MOTOROLA Chapter 11. Secondary (L2) Cache Support 11-7
Part III. The Hardware Interface
11.2 L2 Cache Interface Parameters
The L2 cache interface parameters in the bus conÞguration register (BCR) control the
conÞguration and operation of the MPC8260Õs L2 interface. The parameters should be
conÞgured as follows:
¥ BCR[EBM] = 1ÑMPC8260 in 60x-compatible mode.
¥ BCR[L2C] = 1ÑL2 cache is present.
¥ BCR[L2D] = 0ÑL2 response time. In this case, the L2 will claim a bus transaction
one clock cycle after TS assertion.
¥ BCR[APD] = 1: This parameter is not L2 speciÞc, but should consider the L2
ARTRY assertion timing.
See Section 4.3.2.1, ÒBus ConÞguration Register (BCR),Ó for more details about these
parameters.
11.3 System Requirements When Using the L2 Cache
Interface
The following requirements apply to MPC8260-based systems that implement an external
L2 cache:
¥ For systems that use copy-back mode, all cachable memory regions must be marked
as global in the CPUÕs MMU and the CPMÕs RBA. This causes the assertion of the
GBL signal on every cachable transaction. Systems that use write-through mode (or
ECC/Parity mode) have no such restriction.
¥ All cachable memory regions must have a 64-bit port size.
¥ All cachable memory regions must not set the BRx[DR] bit.
¥ All cachable memory regions must not use ECC or parity unless the external L2 is
connected as described in Section 11.1.3, ÒECC/Parity Mode.Ó
¥ All non-cachable memory regions must be marked as caching-inhibited in the
CPUÕs MMU. This causes the assertion of the CI signal on every non-cachable
transaction. Note that the MPC8260Õs internal space (IMMR) and any memory
banks assigned to the local bus are always considered non-cachable.
11.4 L2 Cache Operation
When conÞgured for an L2 cache (BCR[L2C] = 1), the MPC8260 samples the L2_HIT
input signal when the delay time programmed in BCR[L2D] expires. For 60x bus cycles, if
L2_HIT is asserted, the external L2 cache drives AACK and TA to complete the transaction
without the MPC8260 initiating a system memory transfer.
The external L2 cache can assert ARTRY to retry 60x bus cycles, and can request the bus
by asserting BR to perform L2 cast-out operations. The arbiter grants the address and data