Motorola MPC8260 - Manual (Page 818)

29-38 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Table 29-11. ATM Parameter RAM Map
Offset 1 Name Width Description
0x00Ð
0x3F
С С Reserved, should be cleared.
0x40 RCELL_TMP_
BASE
Hword Rx cell temporary base address. Points to a total of 52 bytes reserved dual-
port RAM area used by the CP. Should be 64 byte aligned. User-deÞned offset
from dual-port RAM base. (Recommended address space: 0x3000-0x4000 or
0xB000Ð0xC000)
0x42 TCELL_TMP_BASE Hword Tx cell temporary base address. Points to total of 52 bytes reserved dual-port
RAM area used by the CP. Should be 64-byte aligned. User-deÞned offset from
dual-port RAM base. (Recommended address space: 0x3000Ð0x4000 or
0xB000Ð0xC000)
0x44 UDC_TMP_BASE Hword UDC mode only. Points to a total of 32 bytes reserved dual-port RAM area
used by the CP. Should be 64-byte aligned. User-deÞned offset from dual-port
RAM base. (Recommended address space: 0x3000Ð0x4000 or 0xB000Ð
0xC000)
0x46 INT_RCT_BASE Hword Internal receive connection table base. User-deÞned offset from dual-port
RAM base.
0x48 INT_TCT_BASE Hword Internal transmit connection table base. User-deÞned offset from dual-port
RAM base.
0x4A INT_TCTE_BASE Hword Internal transmit connection table extension base. User-deÞned offset from
dual-port RAM base.
0x4C Ñ Word Reserved, should be cleared.
0x50 EXT_RCT_BASE Word External receive connection table base. User-deÞned.
0x54 EXT_TCT_BASE Word External transmit connection table base. User-deÞned.
0x58 EXT_TCTE_BASE Word External transmit connection table extension base. User-deÞned.
0x5C UEAD_OFFSET Hword User-deÞned cells mode only. Offset to the user-deÞned extended address
(UEAD) in the UDC extra header. Must be an even address. See
Section 29.10.1.1, ÒDetermining UEAD_OFFSET (UEAD Mode Only).Ó
If RCT[BO] = 01, UEAD_OFFSET should be in little-endian format. For
example, if the UEAD entry is the Þrst half word of the extra header in external
memory, UEAD_OFFSET should be programmed to 2 (second half word entry
in dual-port RAM).
0x5E Ñ Hword Reserved, should be cleared.
0x60 PMT_BASE Hword Performance monitoring table base. User-deÞned offset from dual-port RAM
base.
0x62 APCP_BASE Hword APC parameter table base address. User-deÞned offset from dual-port RAM
base.
0x64 FBT_BASE Hword Free buffer pool parameter table base. User-deÞned offset from dual-port RAM
base.
0x66 INTT_BASE Hword Interrupt queue parameter table base. User-deÞned offset from dual-port RAM
base.
0x68 С С Reserved, should be cleared.
0x6A UNI_STATT_BASE Hword UNI statistics table base. User-deÞned offset from dual-port RAM base.