Motorola MPC8260 - Manual (Page 11)

MOTOROLA Contents xi
CONTENTS
Paragraph
Number
Title
Page
Number
8.4.3.1 Transfer Type Signal (TT[0Ð4]) Encoding ................................................8-10
8.4.3.2 Transfer Code Signals TC[0Ð2] .................................................................8-13
8.4.3.3 TBST and TSIZ[0Ð3] Signals and Size of Transfer...................................8-13
8.4.3.4 Burst Ordering During Data Transfers.......................................................8-14
8.4.3.5 Effect of Alignment on Data Transfers......................................................8-14
8.4.3.6 Effect of Port Size on Data Transfers ........................................................8-16
8.4.3.7 60x-Compatible Bus ModeÑSize Calculation..........................................8-19
8.4.3.8 Extended Transfer Mode............................................................................8-20
8.4.4 Address Transfer Termination .......................................................................8-23
8.4.4.1 Address Retried with ARTRY ...................................................................8-23
8.4.4.2 Address Tenure Timing Configuration ......................................................8-25
8.4.5 Pipeline Control .............................................................................................8-26
8.5 Data Tenure Operations .....................................................................................8-26
8.5.1 Data Bus Arbitration ......................................................................................8-26
8.5.2 Data Streaming Mode ....................................................................................8-27
8.5.3 Data Bus Transfers and Normal Termination ................................................8-27
8.5.4 Effect of ARTRY Assertion on Data Transfer and Arbitration .....................8-28
8.5.5 Port Size Data Bus Transfers and PSDVAL Termination .............................8-28
8.5.6 Data Bus Termination by Assertion of TEA..................................................8-30
8.6 Memory CoherencyÑMEI Protocol..................................................................8-31
8.7 Processor State Signals.......................................................................................8-32
8.7.1 Support for the lwarx/stwcx. Instruction Pair ................................................8-33
8.7.2 TLBISYNC Input...........................................................................................8-33
8.8 Little-Endian Mode ............................................................................................8-33
Chapter 9
Clocks and Power Control
9.1 Clock Unit ............................................................................................................9-1
9.2 Clock Configuration.............................................................................................9-2
9.3 External Clock Inputs...........................................................................................9-5
9.4 Main PLL .............................................................................................................9-5
9.4.1 PLL Block Diagram .........................................................................................9-5
9.4.2 Skew Elimination .............................................................................................9-6
9.5 Clock Dividers......................................................................................................9-6
9.6 The MPC8260Õs Internal Clock Signals...............................................................9-6
9.6.1 General System Clocks ....................................................................................9-7
9.7 PLL Pins...............................................................................................................9-7