Motorola MPC8260 - Manual (Page 452)

13-22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
13.6.5 SET TIMER Command
The SET TIMER command is used to enable, disable, and conÞgure the 16 timers in the RISC
timer table and is issued to the CPCR. This means the value 0x29E1008 should be written
to CPCR. However, before writing this value, the user should program the TM_CMD Þelds.
See Section 13.6.2, ÒRISC Timer Command Register (TM_CMD).Ó
13.6.6 RISC Timer Initialization Sequence
The following sequence initializes the RISC timers:
1. ConÞgure RCCR to determine the preferred tick interval for the entire timer table.
The TIME bit is normally set at this time but can be set later if all RISC timers need
to be synchronized.
2. Determine the maximum number of timers to be located in the timer table.
ConÞgure the TM_BASE in the RISC timer table parameter RAM to point to a
location in the dual-port RAM with 4
´ n bytes available, where n is the number of
timers. If n is less than 16, use timer 0 through timer nÐ1 to save space.
3. Clear the TM_CNT Þeld in the RISC timer table parameter RAM to show how many
ticks elapsed since the RISC internal timer was enabled. This step is optional.
4. Clear RTER, if it is not already cleared. Write ones to clear this register.
5. ConÞgure RTMR to enable the timers that should generate interrupts. Ones enable
interrupts.
6. Set the RISC timer table bit in the SIU interrupt mask register (SIMR_L[RTT]) to
generate interrupts to the system. The SIU interrupt controller may require other
initialization not mentioned here.
7. ConÞgure the TM_CMD Þeld of the RISC timer table parameter RAM. At this
point, determine whether a timer is to be enabled or disabled, one-shot or restart, and
what its timeout period should be. If the timer is being disabled, the parameters
(other than the timer number) are ignored.
8. Issue the SET TIMER command by writing 0x29E1_0008 to the CPCR.
9. Repeat the preceding two steps for each timer to be enabled or disabled.
13.6.7 RISC Timer Initialization Example
The following sequence initializes RISC timer 0 to generate an interrupt approximately
every second using a 133-MHz general system clock:
1. Write 111111 to RCCR[TIMEP] to generate the slowest clock. This value generates
a tick every 64,512 clocks, which is every 485 µs at 133 MHz.
2. ConÞgure the TM_BASE in the RISC timer table parameter RAM to point to a
location in the dual-port RAM with 4 bytes available. Assuming the beginning of
dual-port RAM is available, write 0x0000 to TM_BASE.