Motorola MPC8260 - Manual (Page 131)

MOTOROLA Chapter 3. Memory Map 3-11
Part I. Overview
SCC3
11A40 GSMR_L3 SCC3 general mode register 32 bits 19.1.1/19-3
11A44 GSMR_H3 SCC3 general mode register 32 bits
11A48 PSMR3 SCC3 protocol-speciÞc mode register 16 bits 19.1.2/19-9
20.16/20-13 (UART)
21.8/21-7 (HDLC)
22.11/22-10 (BISYNC)
23.9/23-9 (Transparent)
24.17/24-15 (Ethernet)
11A4A Reserved Ñ 2 bytes Ñ
11A4C TODR3 SCC3 transmit on demand register 16 bits 19.1.4/19-9
11A4E DSR3 SCC3 data synchronization register 16 bits 19.1.3/19-9
11A50 SCCE3 SCC3 event register 16 bits 20.19/20-19 (UART)
21.11/21-12 (HDLC)
22.14/22-15 (BISYNC)
23.12/23-12 (Transparent)
24.20/24-21 (Ethernet)
11A54 SCCM3 SCC3 mask register 16 bits
11A57 SCCS3 SCC3 status register 8 bits 20.20/20-21 (UART)
21.12/21-14 (HDLC)
22.15/22-16 (BISYNC)
23.13/23-13 (Transparent)
11A58Ð11A5F Reserved Ñ 8 bytes Ñ
SCC4
11A60 GSMR_L4 SCC4 general mode register 32 bits 19.1.1/19-3
11A64 GSMR_H4 SCC4 general mode register 32 bits
11A68 PSMR4 SCC4 protocol-speciÞc mode register 16 bits 19.1.2/19-9
20.16/20-13 (UART)
21.8/21-7 (HDLC)
22.11/22-10 (BISYNC)
23.9/23-9 (Transparent)
24.17/24-15 (Ethernet)
11A6A Reserved Ñ 2 bytes Ñ
11A6C TODR4 SCC4 transmit on-demand register 16 bits 19.1.4/19-9
11A6E DSR4 SCC4 data synchronization register 16 bits 19.1.3/19-9
11A70 SCCE4 SCC4 event register 16 bits 20.19/20-19 (UART)
21.11/21-12 (HDLC)
22.14/22-15 (BISYNC)
23.12/23-12 (Transparent)
24.20/24-21 (Ethernet)
11A74 SCCM4 SCC4 mask register 16 bits
Table 3-1. Internal Memory Map (Continued)
Internal
Address
Abbreviation Name Size Section/Page Number