Motorola MPC8260 - Manual (Page 90)

2-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
Figure 2-1. MPC8260 Integrated Processor Core Block Diagram
The processor core is a superscalar processor that can issue and retire as many as three
instructions per clock. Instructions can execute out of order for increased performance;
however, the processor core makes completion appear sequential.
FPR File
FPR
Rename
Registers
Branch
Processing
Unit
Instruction Unit
Integer
Unit
16-Kbyte
D Cache
Tags
Sequential
Fetcher
CTR
CR
LR
+ * /
60x Bus
Interface
Data MMU
SRs
DTLB
DBAT
Array
Touch Load Buffer
Copyback Buffer
64 Bit
32 Bit
Dispatch Unit
64 Bit
Power
Dissipation
Control
Completion
Unit
Time Base
Counter/
Decrementer
Clock
Multiplier
JTAG/COP
Interface
XER
Instruction MMU
SRs
ITLB
IBAT
Array
16-Kbyte
I Cache
Tags
64 Bit
64 Bit
64 Bit
64 Bit 32 Bit
GPR File
Load/Store
Unit
+
64 Bit
GPR
Rename
Registers
Instruction
Queue
64-Bit Data Bus
32-Bit Address Bus
System
Register
Unit
+