Motorola MPC8260 - Manual (Page 781)

MOTOROLA Chapter 29. ATM Controller 29-1
Chapter 29
ATM Controller
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The ATM controller provides the ATM and AAL layers of the ATM protocol using the
universal test and operations physical layer (PHY) interface for ATM (UTOPIA level II) for
both master and slave modes. It performs segmentation and reassembly (SAR) functions of
AAL5, AAL1, and AAL0, and most of the common parts of the convergence sublayer (CP-
CS) of these protocols.
For each virtual channel (VC), the controllerÕs ATM pace control (APC) unit generates a
cell transmission rate to implement constant bit rate (CBR), variable bit rate (VBR),
available bit rate (ABR), unspeciÞed bit rate (UBR) or UBR+ trafÞc. To regulate VBR
trafÞc, the APC unit performs a continuous-state leaky bucket algorithm. The APC unit also
uses up to eight priority levels to prioritize real-time ATM channels, such as CBR and real-
time VBR, over non-real-time ATM channels such as VBR, ABR and UBR.
The ATM controller performs the ATM Forum (UNI-4.0) ABR ßow control. To perform
feedback rate adaptation, it supports forward and backward resource management (RM)
cell generation and ATM Forum ßoating-point calculation. ABR ßow control is
implemented in hardware and Þrmware (without software intervention) to prevent potential
delays during backward RM cell processing and feedback rate adaptation.
The MPC8260 supports a special mode for ATM/TDM interworking. The CPM performs
automatic data forwarding between ATM channels and the MCCsÕ TDM channels without
core intervention.
The MPC8260 ATM SAR controller applications are as follows:
¥ ATM line card controllers
¥ ATM-to-WAN interworking (frame relay, T1/E1 circuit emulation)
¥ Residential broadband network interface units (NIU) (ATM-to-Ethernet)
¥ High-performance ATM network interface cards (NIC)
¥ Bridges and routers with ATM interface