Motorola MPC8260 - Manual (Page 922)

32-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
32.1 Features
The following is a list of the transparent controllerÕs important features:
¥ Flexible data buffers
¥ Automatic SYNC detection on receive
Ñ 16-bit pattern
Ñ 8-bit pattern
Ñ Automatic sync (always synchronized)
Ñ External sync signal support
¥ CRCs can optionally be transmitted and received
¥ Reverse data mode
¥ Another protocol can be performed on the FCCÕs other half (transmitter or receiver)
during transparent mode
¥ External BD table
32.2 Transparent Channel Operation
The transparent transmitter and receiver operates in the same way as the HDLC controller
of the FCC (see Chapter 31, ÒFCC HDLC ControllerÓ) except in the following ways:
1. The FPSMR does not affect the transparent controller, only the GFMR does.
2. In Table 31-1, MFLR, HMASK, RFTHR, and RFCNT must be cleared for proper
operation of the transparent receiver.
3. Transmitter synchronization has to be achieved using CTS before the transmitter
begins sending; see Section 32.3, ÒAchieving Synchronization in Transparent
Mode.Ó
32.3 Achieving Synchronization in Transparent Mode
Once the FCC transmitter is enabled for transparent operation in the GFMR, the TxBD is
prepared for the FCC, and the transmit FIFO is preloaded by the SDMA channel, another
process must occur before data can be transmitted. It is called transmit synchronization.
Similarly, once the FCC receiver is enabled for transparent operation in the GFMR and the
RxBD is made empty for the FCC, receive synchronization must occur before data can be
received. The synchronization process gives the user bit-level control of when the
transmission and reception begins. The methods for this are as follows:
¥ An in-line synchronization pattern
¥ External synchronization signals
¥ Automatic sync