Motorola MPC8260 - Manual (Page 39)

MOTOROLA Illustrations xxxix
ILLUSTRATIONS
Figure
Number
Title
Page
Number
19-2 GSMR_HÑGeneral SCC Mode Register (High Order) ......................................... 19-3
19-3 GSMR_LÑGeneral SCC Mode Register (Low Order) .......................................... 19-6
19-4 Data Synchronization Register (DSR)..................................................................... 19-9
19-5 Transmit-on-Demand Register (TODR).................................................................. 19-9
19-6 SCC Buffer Descriptors (BDs) .............................................................................. 19-11
19-7 SCC BD and Buffer Memory Structure................................................................. 19-12
19-8 Function Code Registers (RFCR and TFCR) ........................................................ 19-15
19-9 Output Delay from RTS Asserted for Synchronous Protocols .............................. 19-18
19-10 Output Delay from CTS Asserted for Synchronous Protocols .............................. 19-19
19-11 CTS Lost in Synchronous Protocols...................................................................... 19-20
19-12 Using CD to Control Synchronous Protocol Reception ........................................ 19-21
19-13 DPLL Receiver Block Diagram............................................................................. 19-22
19-14 DPLL Transmitter Block Diagram ........................................................................ 19-23
19-15 DPLL Encoding Examples .................................................................................... 19-25
20-1 UART Character Format ......................................................................................... 20-1
20-2 Two UART Multidrop Configurations .................................................................... 20-8
20-3 Control Character Table .......................................................................................... 20-9
20-4 Transmit Out-of-Sequence Register (TOSEQ)...................................................... 20-10
20-5 Asynchronous UART Transmitter......................................................................... 20-11
20-6 Protocol-Specific Mode Register for UART (PSMR)........................................... 20-14
20-7 SCC UART Receiving using RxBDs .................................................................... 20-16
20-8 SCC UART Receive Buffer Descriptor (RxBD)................................................... 20-17
20-9 SCC UART Transmit Buffer Descriptor (TxBD) ................................................. 20-18
20-10 SCC UART Interrupt Event Example ................................................................... 20-20
20-11 SCC UART Event Register (SCCE) and Mask Register (SCCM)........................ 20-20
20-12 SCC Status Register for UART Mode (SCCS) ..................................................... 20-21
21-1 HDLC Framing Structure ........................................................................................ 21-2
21-2 HDLC Address Recognition.................................................................................... 21-5
21-3 HDLC Mode Register (PSMR) ............................................................................... 21-7
21-4 SCC HDLC Receive Buffer Descriptor (RxBD)..................................................... 21-8
21-5 SCC HDLC Receiving Using RxBDs ................................................................... 21-10
21-6 SCC HDLC Transmit Buffer Descriptor (TxBD) ................................................. 21-11
21-7 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ........................... 21-12
21-8 SCC HDLC Interrupt Event Example ................................................................... 21-13
21-9 SCC HDLC Status Register (SCCS) ..................................................................... 21-14
21-10 Typical HDLC Bus Multimaster Configuration .................................................... 21-18
21-11 Typical HDLC Bus Single-Master Configuration ................................................. 21-19
21-12 Detecting an HDLC Bus Collision ........................................................................ 21-20
21-13 Nonsymmetrical Tx Clock Duty Cycle for Increased Performance ...................... 21-21
21-14 HDLC Bus Transmission Line Configuration ....................................................... 21-21
21-15 Delayed RTS Mode ............................................................................................... 21-22
21-16 HDLC Bus TDM Transmission Line Configuration ............................................. 21-22
22-1 Classes of BISYNC Frames..................................................................................... 22-1