Motorola MPC8260 - Manual (Page 6)

vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
1.7.2 Bus Configurations .........................................................................................1-15
1.7.2.1 Basic System ..............................................................................................1-15
1.7.2.2 High-Performance Communication ...........................................................1-16
1.7.2.3 High-Performance System Microprocessor ...............................................1-17
Chapter 2
PowerPC Processor Core
2.1 Overview ..............................................................................................................2-1
2.2 PowerPC Processor Core Features ......................................................................2-3
2.2.1 Instruction Unit.................................................................................................2-5
2.2.2 Instruction Queue and Dispatch Unit ...............................................................2-5
2.2.3 Branch Processing Unit (BPU).........................................................................2-6
2.2.4 Independent Execution Units ...........................................................................2-6
2.2.4.1 Integer Unit (IU)...........................................................................................2-6
2.2.4.2 Load/Store Unit (LSU) .................................................................................2-7
2.2.4.3 System Register Unit (SRU) ........................................................................2-7
2.2.5 Completion Unit ...............................................................................................2-7
2.2.6 Memory Subsystem Support ............................................................................2-8
2.2.6.1 Memory Management Units (MMUs) .........................................................2-8
2.2.6.2 Cache Units ..................................................................................................2-8
2.3 Programming Model.............................................................................................2-8
2.3.1 Register Set.......................................................................................................2-8
2.3.1.1 PowerPC Register Set ..................................................................................2-9
2.3.1.2 MPC8260-Specific Registers .....................................................................2-11
2.3.1.2.1 Hardware Implementation-Dependent Register 0 (HID0) .....................2-11
2.3.1.2.2 Hardware Implementation-Dependent Register 1 (HID1) .....................2-14
2.3.1.2.3 Hardware Implementation-Dependent Register 2 (HID2) .....................2-15
2.3.1.2.4 Processor Version Register (PVR) .........................................................2-16
2.3.2 PowerPC Instruction Set and Addressing Modes...........................................2-16
2.3.2.1 Calculating Effective Addresses ................................................................2-16
2.3.2.2 PowerPC Instruction Set ............................................................................2-16
2.3.2.3 MPC8260 Implementation-Specific Instruction Set ..................................2-18
2.4 Cache Implementation........................................................................................2-18
2.4.1 PowerPC Cache Model...................................................................................2-18
2.4.2 MPC8260 Implementation-Specific Cache Implementation..........................2-19
2.4.2.1 Data Cache .................................................................................................2-19
2.4.2.2 Instruction Cache........................................................................................2-21
2.4.2.3 Cache Locking............................................................................................2-21
2.4.2.3.1 Entire Cache Locking.............................................................................2-21
2.4.2.3.2 Way Locking ..........................................................................................2-21
2.5 Exception Model.................................................................................................2-22