Motorola MPC8260 - Manual (Page 91)

MOTOROLA Chapter 2. PowerPC Processor Core 2-3
Part I. Overview
The processor core integrates four execution unitsÑan integer unit (IU), a branch
processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The
ability to execute four instructions in parallel and the use of simple instructions with rapid
execution times yield high efÞciency and throughput. Most integer instructions execute in
one clock cycle.
The processor core supports integer data types of 8, 16, and 32 bits, and ßoating-point data
types of 32 and 64 bits. Note that although the MPC8260 does not implement a ßoating-
point arithmetic unit, it does retain the 32 architecturally-deÞned ßoating point registers
(FPRs), which can be used to hold 32, 64-bit operands that can in turn be transferred to and
from the 32 general-purpose registers (GPRs), which can hold 32, 32-bit operands.
The processor core provides separate on-chip, 16-Kbyte, four-way set-associative,
physically addressed caches for instructions and data and on-chip instruction and data
memory management units (MMUs). The MMUs contain 64-entry, two-way set-
associative, data and instruction translation lookaside buffers (DTLB and ITLB) that
provide support for demand-paged virtual memory address translation and variable-sized
block translation. The TLBs and caches use a least recently used (LRU) replacement
algorithm. The processor core also supports block address translation through the use of
two independent instruction and data block address translation (IBAT and DBAT) arrays of
four entries each. Effective addresses are compared simultaneously with all four entries in
the BAT array during block translation. In accordance with the PowerPC architecture, if an
effective address hits in both the TLB and BAT array, the BAT translation takes priority.
As an added feature to the MPC603e core, the MPC8260 can lock the contents of 1Ð3 ways
in the instruction and data cache (or an entire cache). For example, this allows embedded
applications to lock interrupt routines or other important (time-sensitive) instruction
sequences into the instruction cache. It allows data to be locked into the data cache, which
may be important to code that must have deterministic execution.
The processor core has a 60x bus that incorporates a 64-bit data bus and a 32-bit address
bus. The processor core supports single-beat and burst data transfers for memory accesses
and supports memory-mapped I/O operations.
2.2 PowerPC Processor Core Features
This section describes the major features of the processor core:
¥ High-performance, superscalar microprocessor
Ñ As many as three instructions issued and retired per clock cycle
Ñ As many as four instructions in execution per clock cycle
Ñ Single-cycle execution for most instructions