Motorola MPC8260 - Manual (Page 532)

18-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
¥ Last phase. The remaining data is read into the transfer buffer in bursts, with the last
1Ð31 bytes read in single accesses. All data in the transfer buffer is written to the
destination bus in bursts, with the last 1Ð31 bytes written in single accesses. The last
transfers, read/write or both can be accompanied with DONE assertion, if
programmed.
Figure 18-6 shows an example of the three IDMA transfer stages.
Figure 18-6. Example IDMA Transfer Buffer States for a Memory-to-Memory
Transfer (Size = 128 Bytes)
18.5.1.1 External Request Mode
Memory-to-memory transfers can be conÞgured to operate in external request mode
(DCM[ERM] = 1). In external request mode, every read transfer is triggered by the
assertion of DREQ. When the transfer buffer is full, the Þrst write transfer is done
automatically. Additional write transfers, if needed, are triggered by DREQ assertions.
First Phase
after first read after first write
after second read after second write after third read after third write
Steady-State Phase (2 transfers in this case)
Last Phase
after last read after last write
Read size = EOB(source) + SS_MAX
Write size = EOB(destination) + SS_MAX
Read size = SS_MAX
Write size = SS_MAX
Read size = remainder data of BD
Write size = all data left
EOB (source) EOB (destination)
0
32
64
96
128
Read size = SS_MAX
Write size = SS_MAX
Note: After phase 1, less than 32 bytes (a burst) will
remain in the internal buffer.