Motorola MPC8260 - Manual (Page 105)

2-17 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
¥ Load/store instructionsÑThese include integer and ßoating-point load and store
instructions.
Ñ Integer load and store
Ñ Integer load and store with byte reverse
Ñ Integer load and store string/multiple
Ñ Floating-point load and store. Setting MSR[FPE] allows the MPC8260 to access
the FPRs with the ßoating-point load and store instructions described in the
MPC603e UserÕs Manual. This is useful both for systems that require emulation
of ßoating-point instructions and for increasing data throughput.
¥ Flow control instructionsÑThese include branching instructions, condition register
logical instructions, trap instructions, and other synchronizing instructions that
affect the instruction Яow.
С Branch and trap
Ñ Condition register logical
Ñ Primitives used to construct atomic memory operations (lwarx and stwcx.)
Ñ Synchronize
¥ Processor control instructionsÑThese instructions are used for synchronizing
memory accesses and management of caches, TLBs, and the segment registers.
Ñ Move to/from SPR
Ñ Move to/from MSR
Ñ Instruction synchronize
¥ Memory control instructionsÑThese provide control of caches, TLBs, and segment
registers.
Ñ Supervisor-level cache management
Ñ User-level cache management
Ñ Segment register manipulation
Ñ TLB management
Note that this grouping of the instructions does not indicate which execution unit executes
a particular instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. The PowerPC
architecture uses instructions that are four bytes long and word-aligned. It provides for
byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs.
It also provides for word and double-word operand loads and stores between memory and
a set of 32 ßoating-point registers (FPRs). Although the MPC8260 does use the FPRs for
64-bit loads and stores, it does not support ßoating-point arithmetic instructions.