Motorola MPC8260 - Manual (Page 648)

22-16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Table 22-13 describes SCCE and SCCM Þelds.
22.15 SCC Status Registers (SCCS)
The SCC status (SCCS) register allows real-time monitoring of RXD. The real-time status
of CTS and CD are part of the parallel I/O.
Table 22-13. SCCE/SCCM Field Descriptions
Bits Name Description
0Р2 С Reserved, should be cleared.
3 GLR Glitch on receive. Set when the SCC Þnds an Rx clock glitch.
4 GLT Glitch on transmit. Set when the SCC Þnds a Tx clock glitch.
5 DCC DPLL CS changed. Set when carrier sense status generated by the DPLL changes. Real-time status
can be found in SCCS. This is not the CD status discussed elsewhere. Valid only when DPLL is used.
6Р7 С Reserved, should be cleared.
8 GRA Graceful stop complete. Set as soon the transmitter Þnishes any message in progress when a
GRACEFUL STOP TRANSMIT is issued (immediately if no message is in progress).
9Р10 С Reserved, should be cleared.
11 TXE Tx Error. Set when an error occurs on the transmitter channel.
12 RCH Receive character. Set when a character is received and written to the buffer.
13 BSY Busy. Set when a character is received and discarded due to a lack of buffers. The receiver resumes
reception after an
ENTER HUNT MODE command.
14 TXB Tx buffer. Set when a buffer is sent. TXB is set as the last bit of data or the BCS begins transmission.
15 RXB Rx buffer. Set when the CPM closes the receive buffer on the BISYNC channel.
Bit 0 1 2 3 4 5 6 7
Field Ñ CS Ñ
Reset 0000_0000
R/W R
Addr 0x11A17 (SCCS1); 0x11A37 (SCCS2); 0x11A57 (SCCS3); 0x11A77 (SCCS4)
Figure 22-9. SCC Status Registers (SCCS)