Motorola MPC8260 - Manual (Page 38)

xxxviii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
ILLUSTRATIONS
Figure
Number
Title
Page
Number
14-17 Falling Edge (FE) Effect When CE = 0 and xFSD = 00 ....................................... 14-23
14-18 SIx RAM Shadow Address Registers (SIxRSR) ................................................... 14-24
14-19 SI Command Register (SIxCMDR)....................................................................... 14-24
14-20 SI Status Registers (SIxSTR)................................................................................. 14-25
14-21 Dual IDL Bus Application Example...................................................................... 14-26
14-22 IDL Terminal Adaptor ........................................................................................... 14-27
14-23 IDL Bus Signals..................................................................................................... 14-28
14-24 GCI Bus Signals .................................................................................................... 14-32
15-1 CPM Multiplexing Logic (CMX) Block Diagram .................................................. 15-2
15-2 Enabling Connections to the TSA ........................................................................... 15-4
15-3 Bank of Clocks ........................................................................................................ 15-5
15-4 CMX UTOPIA Address Register (CMXUAR) ....................................................... 15-7
15-5 Connection of the Master Address .......................................................................... 15-8
15-6 Connection of the Slave Address............................................................................. 15-9
15-7 Multi-PHY Receive Address Multiplexing ........................................................... 15-10
15-8 CMX SI1 Clock Route Register (CMXSI1CR)..................................................... 15-11
15-9 CMX SI2 Clock Route Register (CMXSI2CR)..................................................... 15-12
15-10 CMX FCC Clock Route Register (CMXFCR) ...................................................... 15-13
15-11 CMX SCC Clock Route Register (CMXSCR) ...................................................... 15-15
15-12 CMX SMC Clock Route Register (CMXSMR) .................................................... 15-18
16-1 Baud-Rate Generator (BRG) Block Diagram.......................................................... 16-1
16-2 Baud-Rate Generator Configuration Registers (BRGCx) ....................................... 16-2
17-1 Timer Block Diagram .............................................................................................. 17-1
17-2 Timer Cascaded Mode Block Diagram ................................................................... 17-4
17-3 Timer Global Configuration Register 1 (TGCR1)................................................... 17-4
17-4 Timer Global Configuration Register 2 (TGCR2)................................................... 17-5
17-5 Timer Mode Registers (TMR1ÐTMR4) .................................................................. 17-6
17-6 Timer Reference Registers (TRR1ÐTRR4) ............................................................. 17-7
17-7 Timer Capture Registers (TCR1ÐTCR4)................................................................. 17-8
17-8 Timer Counter Registers (TCN1ÐTCN4) ................................................................ 17-8
17-9 Timer Event Registers (TER1ÐTER4)..................................................................... 17-8
18-1 SDMA Data Paths.................................................................................................... 18-1
18-2 SDMA Bus Arbitration (Transaction Steal) ............................................................ 18-3
18-3 SDMA Status Register (SDSR) ............................................................................... 18-3
18-4 SDMA Transfer Error MSNUM Registers (PDTEM/LDTEM).............................. 18-4
18-5 IDMA Transfer Buffer in the Dual-Port RAM........................................................ 18-7
18-6 Example IDMA Transfer Buffer States for a Memory-to-Memory Transfer
(Size = 128 Bytes) ................................................................................................. 18-8
18-7 IDMAx ChannelÕs BD Table................................................................................. 18-15
18-8 DCM Parameters ................................................................................................... 18-18
18-9 IDMA Event/Mask Registers (IDSR/IDMR) ........................................................ 18-23
18-10 IDMA BD Structure .............................................................................................. 18-23
19-1 SCC Block Diagram ................................................................................................ 19-2