Motorola MPC8260 - Manual (Page 225)

MOTOROLA Chapter 7. 60x Signals 7-11
Part III. The Hardware Interface
7.2.5.2 Address Retry (ARTRY)
The address retry (ARTRY) signal is both an input and output signal on the MPC8260
7.2.5.2.1 Address Retry (ARTRY)ÑOutput
.Following are the state meaning and timing comments for ARTRY as an output signal.
State Meaning AssertedÑIndicates that the MPC8260 detects a condition in which
an address tenure must be retried. If the MPC8260 processor needs
to update memory as a result of snoop that caused the retry, the
MPC8260 asserts BR the second cycle after AACK if ARTRY is
asserted.
High ImpedanceÑIndicates that the MPC8260 does not need the
address tenure to be retried.
Timing Comments AssertionÑAsserted the third bus cycle following the assertion of
TS if a retry is required.
NegationÑOccurs the second bus cycle after the assertion of AACK.
Since this signal may be simultaneously driven by multiple devices,
it negates in a unique fashion. First the buffer goes to high impedance
for a minimum of one-half processor cycle (dependent on the clock
mode), then it is driven negated for one bus cycle before returning to
high impedance.
7.2.5.2.2 Address Retry (ARTRY)ÑInput
Following are the state meaning and timing comments for the ARTRY input.
State Meaning AssertedÑIf the MPC8260 is the address bus master, ARTRY
indicates that the MPC8260 must retry the preceding address tenure
and immediately negate BR (if asserted). If the associated data
tenure has started, the MPC8260 also aborts the data tenure
immediately even if the burst data has been received. If the
MPC8260 is not the address bus master, this input indicates that the
MPC8260 should negate BR for one bus clock cycle immediately
after external device asserts ARTRY to permit a copy-back operation
to main memory. Note that the subsequent address presented on the
address bus may not be the one that generated the assertion of
ARTRY.
Negated/High ImpedanceÑIndicates that the MPC8260 does not
need to retry the last address tenure.
Timing Comments AssertionÑMay occur as early as the second cycle following the
assertion of TS and must occur by the bus clock cycle immediately
following the assertion of AACK if an address retry is required.
NegationÑMust occur during the second cycle after the assertion of
AACK.