Motorola MPC8260 - Manual (Page 212)

6-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
L_A24
PCI_REQ1
Local bus address 24ÑLocal bus address bit 24 output pin. In the local address bus bit 14 is most
signiÞcant and bit 31 is least signiÞcant.
PCI arbiter request 1ÑPCI request 1 input pin. When MPC8260Õs internal PCI arbiter is used,
assertion of this pin indicates that an external PCI agent is requesting the PCI bus.
L_A25
PCI_GNT0
Local bus address 25ÑLocal bus address bit 25 output pin. In the local address bus bit 14 is most
signiÞcant and bit 31 is least signiÞcant.
PCI arbiter grant 0ÑPCI grant 0 input/output pin. When MPC8260Õs internal PCI arbiter is used,
this is an output pin. In this mode, assertion of PCI_GNT0 indicates that an the external PCI agent
that requested the PCI bus PCI_REQ0 is granted the bus. When an external PCI arbiter is used,
this is an input pin. In this mode. assertion of PCI_GNT0 indicates that MPC8260Õs PCI interface is
granted the PCI bus.
L_A26
PCI_GNT1
Local bus address 26ÑLocal bus address bit 26 output pin. In the local address bus bit 14 is most
signiÞcant and bit 31 is least signiÞcant.
PCI arbiter grant 1ÑPCI grant 1 output pin. When MPC8260Õs internal PCI arbiter is used,
assertion of PCI_GNT1 indicates that the external PCI agent that requested the PCI bus with
PCI_REQ1 pin is granted the bus.
L_A27
CLKOUT
Local bus address 27ÑLocal bus address bit 27 output pin. In the local address bus bit 14 is most
signiÞcant and bit 31 is least signiÞcant.
Clock OutÑClock output pin. In a PCI system where MPC8260Õs PCI interface is conÞgured to
operate from an external PCI clock, the 60x bus clock is driven on CLKOUT. In a PCI system where
the MPC8260Õs PCI interface is conÞgured to generate the PCI clock, the PCI clock is driven on
CLKOUT. The PCI clock frequency range is 25Ð66 MHz.
L_A28
PCI_RST
CORE_SRESET
Local bus address 28ÑLocal bus address bit 28 output pin. In the local address bus bit 14 is most
signiÞcant and bit 31 is least signiÞcant.
PCI resetÑPCI reset input/output pin. When the MPC8260 is the host in the PCI system, PCI_RST
is an output. When the MPC8260 is not the host of the PCI system, PCI_RST is an input.
Core system resetÑThis is an input to the core. When this input pin is asserted the core branches
to its reset vector.
L_A29
PCI_INTA
Local bus address 29ÑLocal bus address bit 29 output pin. In the local address bus bit 14 is most
signiÞcant and bit 31 is least signiÞcant.
PCI INTAÑ(Input/output) When the MPC8260 is the host in the PCI system, this pin is an input for
delivering PCI interrupts to the host. When the MPC8260 is not the host of the PCI system, this pin
is an output used by the MPC8260 to signal an interrupt to the PCI host.
L_A30 Local bus address 30ÑLocal bus address bit 30 output pin. In the local address bus bit 14 is most
signiÞcant and bit 31 is least signiÞcant.
L_A31
DLLSYNC
Local bus address 31ÑLocal bus address bit 31 output pin. In the local address bus bit 14 is most
signiÞcant and bit 31 is least signiÞcant.
DLLSYNCÑDLL synchronization input. Used to eliminate skew for the clock driven on CLKOUT.
LCL_D[0Ð31]
PCI_AD[0Ð31]
Local bus dataÑLocal bus data input/output pins. In the local data bus bit 0 is most signiÞcant and
bit 31 is least signiÞcant.
PCI address/dataÑPCI bus address/data input/output pins. During an address phase
PCI_AD[0Ð31] contains a physical address, during data phase PCI_AD[0Ð31] contains the data
bytes. In the PCI address/data bus, bit 31 is msb and bit 0 is lsb.
Table 6-1. External Signals (Continued)
Signal Description