Motorola MPC8260 - Manual (Page 94)

2-6 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part I. Overview
are dispatched to their respective execution units from the dispatch unit at a maximum rate
of two instructions per cycle. Reservation stations at the IU, LSU, and SRU facilitate
instruction dispatch to those units. The dispatch unit checks for source and destination
register dependencies, determines dispatch serializations, and inhibits subsequent
instruction dispatching as required. Section 2.7, ÒInstruction Timing,Ó describes instruction
dispatch in detail.
2.2.3 Branch Processing Unit (BPU)
The BPU receives branch instructions from the fetch unit and performs CR lookahead
operations on conditional branches to resolve them early, achieving the effect of a zero-
cycle branch in many cases.
The BPU uses a bit in the instruction encoding to predict the direction of the conditional
branch. Therefore, when an unresolved conditional branch instruction is encountered,
instructions are fetched from the predicted target stream until the conditional branch is
resolved.
The BPU contains an adder to compute branch target addresses and three user-control
registersÑthe link register (LR), the count register (CTR), and the CR. The BPU calculates
the return pointer for subroutine calls and saves it into the LR for certain types of branch
instructions. The LR also contains the branch target address for the Branch Conditional to
Link Register (bclrx) instruction. The CTR contains the branch target address for the
Branch Conditional to Count Register (bcctrx) instruction. The contents of the LR and
CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather
than GPRs or FPRs, execution of branch instructions is largely independent from execution
of other instructions.
2.2.4 Independent Execution Units
The PowerPC architectureÕs support for independent execution units allows
implementation of processors with out-of-order instruction execution. For example,
because branch instructions do not depend on GPRs or FPRs, branches can often be
resolved early, eliminating stalls caused by taken branches.
In addition to the BPU, the processor core provides three other execution units and a
completion unit, which are described in the following sections.
2.2.4.1 Integer Unit (IU)
The IU executes all integer instructions. The IU executes one integer instruction at a time,
performing computations with its arithmetic logic unit (ALU), multiplier, divider, and XER
register. Most integer instructions are single-cycle instructions. Thirty-two general-purpose
registers are provided to support integer operations. Stalls due to contention for GPRs are
minimized by the automatic allocation of rename registers. The processor core writes the
contents of the rename registers to the appropriate GPR when integer instructions are
retired by the completion unit.