Motorola MPC8260 - Manual (Page 489)

MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-35
Part IV. Communications Processor Module
14. Clear PSORB[17]. ConÞgures L1CLKO and L1RQa.
15. Set PDIRB[17]. ConÞgures L1CLKO and L1RQa.
16. If the 1x GCI data clock is required, set PBPAR bit 16 and PBDIR bit 16 and clear
PSORB 16, which conÞgures L1CLKOa as an output.
17. ConÞgure SCC1 for HDLC operation (to handle the LAPD protocol of the D
channel). ConÞgure SMC1 for SCIT operation and conÞgure SCC2 and SMC2 as
preferred.
18. SI1GMR = 0x11. Enable TDMa (one static TDM), STZ for TDMa.
19. SI1CMDR is not used.
20. SI1STR does not need to be read.
21. Enable the SCC1, SCC2, SMC1 and SMC2.