Motorola MPC8260 - Manual (Page 782)

MOTOROLA Chapter 29. ATM Controller 29-2
Part IV. Communications Processor Module
29.1 Features
The ATM controller has the following features:
¥ Full duplex segmentation and reassembly at 155 Mbps
¥ UTOPIA level II master and slave modes 8/16 bit
¥ AAL5, AAL1, AAL0 protocols
¥ Up to 255 active VCs internally, and up to 64K VCs using external memory
¥ TM 4.0 CBR, VBR, UBR, UBR+ trafÞc types
¥ VBR type 1 and 2 trafÞc using leaky buckets (GCRA)
¥ TM 4.0 ABR ßow control (EFCI and ER)
¥ Idle/unassign cells screening/transmission option
¥ External and internal rate transmit modes
¥ Special mode for ATM-to-TDM or ATM-to-ATM data forwarding
¥ CLP and congestion indication marking
¥ User-deÞned cells up to 65 bytes
¥ Separate Tx and RxBD tables for each virtual channel (VC)
¥ Special mode of global free buffer pools for dynamic and efÞcient memory
allocation with early packet discard (EPD) support
¥ Interrupt report per channel using four priority interrupt queues
¥ Compliant with ATMF UNI 4.0 and ITU speciÞcation
¥ AAL5 cell format
Ñ Reassembly
Ð Reassemble PDU directly to external memory
Ð CRC32 check
Ð CLP and congestion report
Ð CPCS_UU, CPI, and length check
Ð Abort message report
Ñ Segmentation
Ð Segment PDU directly from external memory
Ð Performs PDU padding
Ð CRC32 generation
Ð Automatic last cell marking
Ð Automatic CPCS_UU, CPI, and length insertion
Ð Abort message option
¥ AAL1 cell format
Ñ Reassembly
Ð Reassemble PDU directly to external memory
Ð Support for partially Þlled cells (conÞgurable on a per-VC basis)