Motorola MPC8260 - Manual (Page 87)

MOTOROLA Chapter 1. Overview 1-17
Part I. Overview
Serial throughput is enhanced by connecting one MPC8260 in master or slave mode (with
system core enabled or disabled) to another MPC8260 in master mode with the core
enabled. The core in MPC8260 A can access the memory on the local bus of MPC8260 B.
1.7.2.3 High-Performance System Microprocessor
Figure 1-11 shows a conÞguration with a high-performance system microprocessor
(MPC750).
Figure 1-11. High-Performance System Microprocessor Configuration
In this system, the MPC603e core internal is disabled and an external high-performance
microprocessor is connected to the 60x bus.
MPC750
32-Kbyte I cache
32-Kbyte D cache
Backside
Cache
MPC8260 (slave)
Local Bus
SDRAM/SRAM/DRAM
60x Bus
SDRAM/SRAM/DRAM
ATM
Connection Tables
Communication
Channels
UTOPIA
PHY
155 Mbps
PHY ATM