Motorola MPC8260 - Manual (Page 332)

10-56 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
Figure 10-47. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0,TRLX = 1)
When TRLX and CSNT are set in a write-memory access, the strobe lines, WE[0Ð7] are
negated one clock earlier than in the normal case. If ACS
¹ 0, CS is also negated one clock
earlier, as shown in Figure 10-48 and Figure 10-49. When a bank is selected to operate with
external transfer acknowledge (SETA and TRLX = 1), the memory controller does not
support external devices that provide PSDVAL to complete the transfer with zero wait
states. The minimum access duration in this case is three clock cycles.
Figure 10-48 . GPCM Relaxed-Timing Write (ACS = 10, SCY = 0, CSNT = 1, TRLX = 1)
Clock
Address
PSDVAL
CS
R/W
WE
OE
Data
ACS = 10
ACS = 11
Clock
Address
PSDVAL
CS
R/W
WE
OE
Data
ACS = 10 CSNT = 1