Motorola MPC8260 - Manual (Page 472)

14-18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Table 14-5 describes SIxMR Þelds.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ SADx SDMx RFSDx DSCx CRTx SLx CEx FEx GMx TFSDx
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x11B20 (SI1AMR), 0x11B22 (SI1BMR), 0x11B24 (SI1CMR), 0x11B26 (SI1DMR)/
0x11B40 (SI2AMR), 0x11B42 (SI2BMR), 0x11B44 (SI2CMR), 0x11B46 (SI2DMR)
Figure 14-11. SI Mode Registers (SIxMR)
Table 14-5. SIxMR Field Descriptions
Bits Name Description
0 Ñ Reserved. Should be cleared.
1Ð3 SADx Starting bank address for the RAM of TDM a, b, c or d. These three bits deÞne the starting bank
address of the SIx RAM section that belongs to TDMx channel.
Note: As noted previously, the SIx RAM contains four banks of 64 entries for receive and four banks
of 64 entries for transmit. The starting bank address of each TDM can be programmed with a
granularity of 32 entries. The user can put the shadow RAM section of the same TDM on the same
bank, but the user cannot put two different TDMs on the same bank.
The last entry of a certain TDM is determined by the LST bit in the SIx RAM entry. The user must
set LST within the entries of SIx RAM blocks for every TDM used, that is, before the starting
address of the next TDM.
000 Þrst bank, Þrst 32 entries
001 Þrst bank, second 32 entries
010 second bank, Þrst 32entries
011 second bank, second 32 entries
100 third bank, Þrst 32 entries
101 third bank, second 32 entries
110 fourth bank, Þrst 32 entries
111 fourth bank, second 32 entries
4Ð5 SDMx SI Diagnostic Mode for TDM a, b, c or d
00 Normal operation.
01 Automatic echo. In this mode, the TDM transmitter automatically retransmits the TDM received
data on a bit-by-bit basis. The receive section operates normally, but the transmit section can
only retransmit received data. In this mode, the L1GRx line is ignored.
10 Internal loopback. In this mode, the TDM transmitter output is internally connected to the TDM
receiver input (L1TXDx is connected to L1RXDx). The receiver and transmitter operate
normally. The data appears on the L1TXDx pin and in this mode, L1RQx is asserted normally.
The L1GRx line is ignored.
11 Loopback control. In this mode, the TDM transmitter output is internally connected to the TDM
receiver input (L1TXDx is connected to L1RXDx). The transmitter output (L1TXDx) and L1RQx
are inactive. This mode is used to accomplish loopback testing of the entire TDM without
affecting the external serial lines.
Note: In modes 01, 10, and 11, the receive and transmit clocks should be identical.