Motorola MPC8260 - Manual (Page 983)

MOTOROLA Index Index-3
INDEX
system interface unit (SIU)
periodic interrupt timer, 4-5
SIU block diagram, 4-1
software watchdog timer, 4-7
system configuration/protection logic, 4-3
time counter (TMCNT), 4-5
system PLL, 9-5
timers, 17-1
Branch processing unit overview, 2-6
BRGCLK, 34-2
BRn (base registers), 10-14
BSYNC (BISYNC SYNC) register, 22-7
BUFCMD (external address and command
buffers), 10-42
Buffer descriptors
ATM controller
receive, 29-65, 29-69
transmit, 29-64, 29-74
BISYNC mode, 22-12
fast communications controllers (FCCs)
Fast Ethernet mode
receive, 30-23
transmit, 30-26
HDLC mode
receive, 31-9
transmit, 31-12
overview
receive, 28-9
transmit, 28-9
GCI mode
monitor channel, 26-32
HDLC mode, 21-8
I
2 C controller
receive, 34-13
transmit, 34-14
IDMA emulation
auto buffer, 18-15
IDMA buffers, 18-23
multi-channel controllers (MCCs)
receive, 27-21
transmit, 27-23
overview, 19-10
serial management controllers (SMCs), 26-5
serial peripheral interface (SPI)
receive, 33-14
transmit, 33-15
transparent mode
serial communications controllers (SCCs), 23-9
serial management controllers (SMCs), 26-26
UART mode
serial communications controllers (SCCs), 20-15
serial management controllers (SMCs), 26-14
Bus interface
hierarchical bus interface example, 10-100
BxTx (byte-select signals), 10-75
Byte stuffing, 22-1
Byte-select signals, 10-75
C
Cascaded mode, 17-3
CHAMR (channel mode register), 27-10
CHAMR (channel mode register,
transparent mode), 27-13
Chip-select
assertion timing, 10-53
chip-select machine, 10-51
signals, 10-74
write enable deassertion timing, 10-54
Clock glitch detection, 19-26
Clocks
basic power structure, 9-10
clock divider, 9-6
clock unit, 9-1
external clock inputs, 9-5
general system clocks, 9-7
input clock interface, 9-1
internal clock signals, 9-6
main PLL, 9-5
memory map, 3-4
OSCM, 9-1
overview, 9-1
PLL block diagram, 9-5
PLL pins, 9-7
SCC clock glitch detection, 19-26
SCCR, 9-8
SCMR, 9-9
skew elimination, 9-6
CMXFCR (CMX FCC clock route register), 15-12
CMXSCR (CMX SCC clock route register), 15-14
CMXSI1CR (CMX SI1 clock route register), 15-10
CMXSI2CR (CMX SI2 clock route register), 15-11
CMXSMR (CMX SMC clock route register), 15-17
CMXUAR (CMX UTOPIA address register), 15-7
Commands
ATM TRANSMIT command, 29-90
fast communications controllers (FCCs)
Ethernet mode
receive commands, 30-13
transmit commands, 30-12
HDLC mode
receive commands, 31-6
transmit commands, 31-5
I 2 C controller, 34-11
IDMA emulation, 18-26
multi-channel controllers (MCCs)
receive commands, 27-17
serial peripheral interface (SPI), 33-12