Motorola MPC8260 - Manual (Page 73)

MOTOROLA Chapter 1. Overview 1-3
Part I. Overview
Ñ Byte write enables and selectable parity generation
Ñ 32-bit address decodes with programmable bank size
Ñ Three user programmable machines, general-purpose chip-select machine, and
page mode pipeline SDRAM machine
Ñ Byte selects for 64-bit bus width (60x) and for 32-bit bus width (local)
Ñ Dedicated interface logic for SDRAM
¥ Disable CPU mode
¥ Communications processor module (CPM)
Ñ Embedded 32-bit communications processor (CP) uses a RISC architecture for
ßexible support for communications peripherals
Ñ Interfaces to PowerPC core through on-chip 24-Kbyte dual-port RAM and DMA
controller
Ñ Serial DMA channels for receive and transmit on all serial channels
Ñ Parallel I/O registers with open-drain and interrupt capability
Ñ Virtual DMA functionality executing memory to memory and memory to I/O
transfers
Ñ Three fast communication controllers (FCCs) supporting the following protocols
Ð 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media
independent interface (MII)
Ð ATMÑfull-duplex SAR at 155 Mbps, UTOPIA interface, AAL5, AAL1,
AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR trafÞc types, up to 64 K
external connections
Ð Transparent
Ð HDLCÑup to T3 rates (clear channel)
Ñ Two multichannel controllers (MCCs)
Ð Two 128 serial full-duplex data channels (for a total of 256 64 Kbps channels).
Each MCC can be split into four subgroups of 32 channels each.
Ð Almost any combination of subgroups can be multiplexed to single or
multiple TDM interfaces
Ñ Four serial communications controllers (SCCs) identical to those on the
MPC860, supporting the digital portions of the following protocols:
Ð Ethernet/IEEE 802.3 CDMA/CS
Ð HDLC/SDLC and HDLC bus
Ð Universal asynchronous receiver transmitter (UART)
Ð Synchronous UART
Ð Binary synchronous (BiSync) communications
Ð Transparent