Motorola MPC8260 - Manual (Page 224)

7-10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
NegatedÑIndicates that the transaction should not operate in write-
through mode.
Timing Comments Assertion/NegationÑSame as A[0Ð31].
High ImpedanceÑSame as A[0Ð31].
7.2.5 Address Transfer Termination Signals
The address transfer termination signals are used to indicate either that the address phase
of the transaction has completed successfully or must be repeated, and when it should be
terminated. For detailed information about how these signals interact, see Section 7.2.5,
ÒAddress Transfer Termination Signals.Ó
The address transfer termination signals have no meaning in internal only mode.
7.2.5.1 Address Acknowledge (AACK)
The address acknowledge (AACK) signal is an input/output on the MPC8260.
7.2.5.1.1 Address Acknowledge (AACK)ÑOutput
.Following are the state meaning and timing comments for AACK as an output signal.
State Meaning AssertedÑIndicates that the address tenure of a transaction is
terminated. On the cycle following the assertion of AACK, the bus
master releases the address-tenure-related signals to the high-
impedance state and samples ARTRY.
NegatedÑIndicates that the address bus and the transfer attributes
must remain driven, if negated during ABB.
Timing Comments AssertionÑOccurs a programmable number of clocks after TS or
whenever ARTRY conditions are resolved.
NegationÑOccurs one clock after assertion.
7.2.5.1.2 Address Acknowledge (AACK)ÑInput
Following are the state meaning and timing comments for AACK as an input signal.
State Meaning AssertedÑIndicates that a 60x bus slave is terminating the address
tenure. On the cycle following the assertion of AACK, the bus master
releases the address tenure related signals to the high-impedance
state and samples ARTRY.
NegatedÑIndicates that the address tenure must remain active and
the address tenure related signals driven.
Timing Comments AssertionÑOccurs during the 60x bus slave access, at least two
clocks after TS.
NegationÑOccurs one clock after assertion.