Motorola MPC8260 - Manual (Page 330)

10-54 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
10.5.1.2 Chip-Select and Write Enable Deassertion Timing
Figure 10-43 shows a basic connection between the MPC8260 and a static memory device.
Here, CS is connected directly to CE of the memory device. The WE signals are connected
to the respective W signal in the memory device where each WE corresponds to a different
data byte.
Figure 10-43. GPCM Memory Device Interface
As Figure 10-45 shows, the timing for CS is the same as for the address lines. The strobes
for the transaction are supplied by OE or WE, depending on the transaction direction (read
or write). ORx[CSNT] controls the timing for the appropriate strobe negation in write
cycles. When this attribute is asserted, the strobe is negated one quarter of a clock before
the normal case. For example, when ACS = 00 and CSNT = 1, WE is negated one quarter
of a clock earlier, as shown in Figure 10-44.
Figure 10-44. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0)
When ACS
¹ 00 and CSNT = 1, WE and CS are negated one quarter of a clock earlier, as
shown in Figure 10-45.
Address
CE
OE
W
Data
MEMORY
Data
WE
OE
CS
Address
MPC8260
Clock
Address
PSDVAL
CS
WE
OE
Data
CSNT = 1