Motorola MPC8260 - Manual (Page 119)

MOTOROLA Chapter 2. PowerPC Processor Core 2-31
Part I. Overview
Addition of speed-for-power
functionality The processor core implements an additional dynamic power management
mechanism. HID2[SFP] controls this function. See Section 2.3.1.2.3,
ÒHardware Implementation-Dependent Register 2 (HID2).Ó
Improved access to cache during block
Þlls The MPC8260 provides quicker access to incoming data and instruction on
a cache block Þll. See Section 2.4.2, ÒMPC8260 Implementation-SpeciÞc
Cache Implementation.Ó
Improved integer divide latency Performance of integer divide operations has been improved in the
processor core. A divide takes half the cycles to execute as described in
MPC603e UserÕs Manual. The new latency is reßected in Table 2-6.
Table 2-7. Major Differences between MPC8260Õs Core and the MPC603e UserÕs
Manual
Description Impact