Motorola MPC8260 - Manual (Page 988)

Index-8 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
INDEX
CxTx (chip-select signals), 10-74
D
DCM (IDMA channel mode), 18-18
Digital phase-locked loop (DPLL) operation, 19-22
DSR (data synchronization register)
overview, 19-9
UART mode, 20-11
Dual-port RAM
accessing dual-port RAM, 13-15
block diagram, 13-15
buffer descriptors, 13-17
memory map, 13-16
overview, 13-15
parameter RAM, 13-17
E
EAMUX (external address multiplexing)
signal, 10-41
EDO interface connection, MPC8260 to 60x
bus, 10-92
Ethernet mode
fast communications controller (FCC)
address recognition, 30-15
block diagram, 30-3
CAM interface, 30-8
collision handling, 30-18
connecting to the MPC8260, 30-4
error handling, 30-19
FCCE, 30-21
FCCM, 30-21
features list, 30-3
FPSMR, 30-20
frame reception, 30-7
frame transmission, 30-5
hash table algorithm, 30-17
hash table effectiveness, 30-17
interpacket gap time, 30-18
interrupt events, 30-23
loopback mode, 30-18
parameter RAM, 30-9
programming model, 30-12
registers, 30-19
RMON support, 30-14
RxBD, 30-23
TxBD, 30-26
Exceptions
exception handling, 10-73
overview, 2-22
Execution units, 2-6
F
Fast communications controllers (FCCs)
Fast Ethernet mode
address recognition, 30-15
block diagram, 30-3
CAM interface, 30-8
collision handling, 30-18
connecting to the MPC8260, 30-4
error handling, 30-19
FCCE, 30-21
FCCM, 30-21
features list, 30-3
FPSMR, 30-20
frame reception, 30-7
frame transmission, 30-5
hash table algorithm, 30-17
hash table effectiveness, 30-17
interpacket gap time, 30-18
interrupt events, 30-23
loopback mode, 30-18
parameter RAM, 30-9
programming model, 30-12
registers, 30-19
RMON support, 30-14
RxBD, 30-23
TxBD, 30-26
HDLC mode
bit stuffing, 31-1
error control, 31-1
error handling, 31-6
FCCE, 31-14
FCCM, 31-14
FCCS, 31-16
features list, 31-2
FPSMR, 31-7
frame reception, 31-3
frame transmission, 31-2
overview, 31-1
parameter RAM, 31-4
programming model, 31-5
receive commands, 31-6
reception errors, 31-7
RxBD, 31-9
transmission errors, 31-6
transmit commands, 31-5
TxBD, 31-12
overview
block diagram, 28-3
disabling FCCs, 28-19
FCCEx, 28-14
FCCMx, 28-14
FCCSx, 28-14
FCRx, 28-13
FDSRx, 28-7