Motorola MPC8260 - Manual (Page 235)

MOTOROLA Chapter 8. The 60x Bus 8-3
Part III. The Hardware Interface
Figure 8-1. Single MPC8260 Bus Mode
Note that in single MPC8260 bus mode, the MPC8260 uses the address bus as a memory
address bus. Slaves cannot use the 60x bus signals because the addresses have memory
timing, not address tenure timing.
8.2.2 60x-Compatible Bus Mode
The 60x-compatible bus mode can include one or more potential external masters (for
example, an L2 cache, an ASIC DMA, a high-end PowerPC processor, or a second
MPC8260). When operating in a multiprocessor conÞguration, the MPC8260 snoops bus
operations and maintains coherency between the primary caches and main memory.
Figure 8-2 shows how an external processor is attached to the MPC8260.
TS
A[0Ð31]
TT[0Ð4]
TSIZ[0Ð3]
TBST
CI
WT
GBL
AACK
ARTRY
DBG
D[0Ð63]
DP[0Ð7]
TA
TEA
MPC8260
I/O
MEM
Data + Attributes
Address + Attributes
Latch &
Memory Controller Signals
DRAM MUX
Memory Control Signals
APE