Motorola MPC8260 - Manual (Page 216)

7-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
¥ Data transfer signalsÑThese signals, which consist of the data bus, data parity, and
data parity error signals, transfer the data and ensure its integrity.
¥ Data transfer termination signalsÑData termination signals are required after each
data beat in a data transfer. In a single-beat transaction, the data termination signals
also indicate the end of the tenure. For burst accesses or extended port-size accesses,
the data termination signals apply to individual beats and indicate the end of the
tenure only after the Þnal data beat.
7.1 Signal ConÞguration
Figure shows the grouping of the MPC8260Õs 60x bus signal conÞguration.
NOTE
The MPC8260 hardware speciÞcations provides a pinout
showing pin numbers. These are shown in Figure 7-1.
Figure 7-1. PowerPC Signal Groupings
Bus Request (BR)
Bus Grant (BG)
Address Bus Busy (ABB)
Transfer Start (TS)
Address Parity (AP[0Ð3])
Transfer Size (TSIZ[0Ð3])
Transfer Burst (TBST)
Cache Inhibit (CI)
Write-Through (WT)
Address Acknowledge (AACK)
Address Retry (ARTRY)
Data Bus Grant (DBG)
Data Bus Busy (DBB)
Data (D[0Ð63])
Data Parity (DP[0Ð7])
Transfer Acknowledge (TA)
Transfer Error Acknowledge (TEA)
Reservation
1
1
1
1
1
64
8
1
1
1
4
5
4
1
1
1
1
1
Data
Data
Data
Processor
Address
Address
Address
Transfer
Attributes
Address
ermination
1
Transfer Type (TT[0Ð4])
Global (GBL)
1
TLBI SYNC
1
Partial Data Valid Indication (PSDVAL)
1
3
Transfer Code (TC[0Ð2])
Address (A[0Ð31])
32
Address Parity Enable
1
State
Termination
Transfer
Arbitration
Arbitration
Start
Bus