Motorola MPC8260 - Manual (Page 277)

MOTOROLA Chapter 10. Memory Controller 10-1
Chapter 10
Memory Controller
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The memory controller is responsible for controlling a maximum of twelve memory banks
shared by a high performance SDRAM machine, a general-purpose chip-select machine
(GPCM), and three user-programmable machines (UPMs). It supports a glueless interface
to synchronous DRAM (SDRAM), SRAM, EPROM, ßash EPROM, burstable RAM,
regular DRAM devices, extended data output DRAM devices, and other peripherals. This
ßexible memory controller allows the implementation of memory systems with very
speciÞc timing requirements.
¥ The SDRAM machine provides an interface to synchronous DRAMs, using
SDRAM pipelining, bank interleaving, and back-to-back page mode to achieve the
highest performance.
¥ The GPCM provides interfacing for simpler, lower-performance memory resources
and memory-mapped devices. The GPCM has inherently lower performance
because it does not support bursting. For this reason, GPCM-controlled banks are
used primarily for boot-loading and access to low-performance memory-mapped
peripherals.
¥ The UPM supports address multiplexing of the external bus, refresh timers, and
generation of programmable control signals for row address and column address
strobes to allow for a glueless interface to DRAMs, burstable SRAMs, and almost
any other kind of peripheral. The refresh timers allow refresh cycles to be initiated.
The UPM can be used to generate different timing patterns for the control signals
that govern a memory device. These patterns deÞne how the external control signals
behave during a read, write, burst-read, or burst- write access request. Refresh timers
are also available to periodically generate user-deÞned refresh cycles.
Unless stated otherwise, this chapter describes the 60x bus memory controller. The local
bus memory controller provides the same functionality as the 60x bus memory controller
except 64-bit port size ECC and external master support.