Motorola MPC8260 - Manual (Page 698)

26-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
Figure 26-1. SMC Block Diagram
The receive data source can be L1RXD if the SMC is connected to a TDM channel of an
SIx, or SMRXD if it is connected to the NMSI. The transmit data source can be L1TXD if
the SMC is connected to a TDM or SMTXD if it is connected to the NMSI.
If the SMC is connected to a TDM, the SMC receive and transmit clocks can be
independent from each other, as deÞned in Chapter 14, ÒSerial Interface with Time-Slot
Assigner.Ó However, if the SMC is connected to the NMSI, receive and transmit clocks
must be connected to a single clock source (SMCLK), an internal signal name for a clock
generated from the bank of clocks. SMCLK originates from an external signal or one of the
four internal baud rate generators.
An SMC connected to a TDM derives a synchronization pulse from the TSA. An SMC
connected to the NMSI using transparent protocol can use SMSYN for synchronization to
determine when to start a transfer. SMSYN is not used when the SMC is in UART mode.
26.1 Features
The following is a list of the SMCÕs main features:
¥ Each SMC can implement the UART protocol on its own signals
¥ Each SMC can implement a totally transparent protocol on a multiplexed or
nonmultiplexed line. This mode can also be used for a fast connection between
MPC8260s.
¥ Each SMC channel fully supports the C/I and monitor channels of the GCI (IOM-2)
in ISDN applications
¥ Two SMCs support the two sets of C/I and monitor channels in the SCIT channels 0
and 1
Shifter
SYNC
Rx
Data
Register
Tx
Data
Register
RXD
Control
Logic
TXD
Control
Registers
Shifter
Peripheral Bus
CLK
60x Bus